The present invention relates in general to a power semiconductor package, and more particularly, to a power semiconductor package (e.g., SO8 or QFN) in which a power semiconductor die current carrying electrode is electrically coupled to a leadframe via a clip while the power semiconductor die control electrode is electrically coupled to the leadframe via a ribbon bond.
With reference to FIG. 1 and FIG. 2, a semiconductor package 10 according to the prior art is shown as presented in U.S. Pat. No. 6,040,626. The semiconductor package 10 includes a bottom plate portion 13 and terminals 12a, 12b and 18. A semiconductor die 16 includes a first metalized region 19 (typically aluminum) defining a first connection area for a top surface of the semiconductor die 16, and a second metalized region 15 (typically aluminum) defining a second connection area for the top surface of the semiconductor die 16. Portions of the terminals 12a, 12b, 18, bottom plate 13, and semiconductor die 16 are encapsulated in a housing 22, typically formed from a moldable material.
In order to obtain an electrical connection between the first metalized region 19 and the terminal(s) 12b, a clip 17 is attached at one end 17a to the first metalized region 19 and at a distal end 17b to the terminal(s) 12b. Clip 17 is typically made from fairly rigid copper and optionally silver plated for either solder attachment or conductive epoxy attachment. The electrical connection between the second metalized region 15 and the terminal 12a is obtained by ultrasonically attaching a wirebond bond 14 by end 14a to second metalized region 15 and wirebond 14 end 14b to terminal 12a. 
It is desirable to significantly reduce the resistance and the inductance of current paths through a power semiconductor package in order to ensure optimum electrical performance of the semiconductor device, as well as to minimize or reduce the overall footprint 23 and thickness 24 of semiconductor package 10 to improve heat removal to allow for increased power operation. Unfortunately, the semiconductor packages of the prior art do not fully achieve these objectives because, among other things, the area of the metalized region or gate contact 15 must be sufficiently large to accommodate wirebond 14 attachment, which in turn detrimentally reduces the area of the metalized region or source contact 19 as will be shown below.
As well known in the art, attachment of wirebond 14 typically includes forming a wirebond ball on wirebond 14 end 14a for attachment to gate contact 15 and a wirebond stitch on wirebond 14 end 14b for attachment to terminal 12a. In general, the dimensions of gate contact 15 which determine its area are typically selected to be approximately five times the diameter of wirebond 14, as the wirebond ball is approximately three times the diameter of wirebond 14. As the diameter of wirebond 14 becomes smaller, for example in the range below one hundred twenty five micrometers (“microns”) the wirebond becomes frail, difficult to form or handle, requires more expensive manufacturing equipment and is subject to shock and mechanical stresses, which increases undesirable failure of the electrical connection and thus the device. Even at what is currently considered as the practical low cost wirebond diameter limit wherein diameters such as fifty microns are employed (smaller than this is considered impractical due to at least the above frailty, reliability and cost concerns), a significantly large gate metal contact 15 area is still required of about sixty two thousand five hundred square microns in area (five times fifty microns by five times fifty microns). Thus, the area available for metalized region or source metal contact 19 on a die of about five thousand microns by five thousand microns would be about seventeen million and sixty two thousand five hundred square microns (allowing about five hundred microns for streets, such as between metal contacts and the edge of the die) or about sixty eight percent of the available die area. Thus, as die area or size is expected to become smaller while the size of the wire bond gate contact is for practical purposes fixed in size at about sixty two thousand five hundred square microns or larger, the source metal area will decrease correspondingly.
Large clip 17 is used to enable high power operation such as generated by large source current IS, as well as to improve heat removal. Furthermore, large clip 17 desirably decreases resistance and inductance. Large clip 17 requires a large metal area to make appropriate connection. Therefore, as the source metal area is the largest source of thermal radiation or heat needing to be removed from the die, finding ways to maximize the source metal area for a given die size is an imperative for increasing power ratings while producing smaller packaged semiconductor devices.
Additionally, even when employing small wirebond 14 diameters such as fifty microns, the thickness 24 of semiconductor package 24 must be sufficiently thick in order to allow for the height WBH of wirebond 14 to be covered by mold compound 22. Unfortunately, wirebond height WBH presents a constraint on decreasing thickness 24 of the packaged semiconductor device to additionally improve removal of heat from the die by having minimal mold compound over the die.
Fundamentally, the area or footprint 23 required to mount the power semiconductor package is also determined in part by the area of the metalized region or source metal contact 19 and metalized region or gate metal contact 15, as the smaller the die the smaller the footprint. As above, the area of gate metal contact 15 is fairly fixed, thus further die size reductions will come at the detrimental expense of reducing the area of source metal contact 19 so important to electrical and thermal performance, thus power rating.
Thus, problems associated with decreased source metal area will become further exacerbated as future requirements for smaller and smaller die having increased power and thermal operating requirements.
Hence, there is a need for a power semiconductor device and package having a small footprint, high current and thermal dissipation capability and a high reliability while maintaining a low manufacturing cost.